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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 12 | jlesech | 1 | /**************************************************************************//** |
| 2 | * \brief USART0 library |
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| 3 | * \author Copyright (C) 2011 Julien Le Sech - www.idreammicro.com |
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| 4 | * \version 1.0 |
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| 5 | * \date 20090426 |
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| 6 | * |
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| 7 | * This file is part of the iDreamMicro library. |
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| 8 | * |
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| 9 | * This library is free software: you can redistribute it and/or modify it under |
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| 10 | * the terms of the GNU Lesser General Public License as published by the Free |
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| 11 | * Software Foundation, either version 3 of the License, or (at your option) any |
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| 12 | * later version. |
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| 13 | * |
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| 14 | * This library is distributed in the hope that it will be useful, but WITHOUT |
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| 15 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS |
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| 16 | * FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more |
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| 17 | * details. |
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| 18 | * |
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| 19 | * You should have received a copy of the GNU Lesser General Public License |
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| 20 | * along with this program. If not, see http://www.gnu.org/licenses/ |
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| 21 | ******************************************************************************/ |
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| 22 | |||
| 23 | /**************************************************************************//** |
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| 24 | * \file usart0_m328.c |
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| 25 | ******************************************************************************/ |
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| 26 | |||
| 27 | /****************************************************************************** |
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| 28 | * Header file inclusions. |
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| 29 | ******************************************************************************/ |
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| 30 | |||
| 31 | #include "../usart0.h" |
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| 32 | |||
| 33 | #include <usart/usart.h> |
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| 34 | |||
| 35 | #include <useful/bits.h> |
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| 36 | |||
| 37 | #include <avr/interrupt.h> |
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| 38 | #include <avr/io.h> |
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| 39 | |||
| 40 | #include <assert.h> |
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| 23 | jlesech | 41 | #include <stdbool.h> |
| 12 | jlesech | 42 | #include <stdint.h> |
| 43 | #include <stdlib.h> |
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| 44 | |||
| 45 | /****************************************************************************** |
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| 46 | * Private variable declarations. |
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| 47 | ******************************************************************************/ |
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| 48 | |||
| 49 | static usart__rx_complete_callback_t* p_rx_complete = NULL; |
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| 50 | static usart__tx_complete_callback_t* p_tx_complete = NULL; |
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| 51 | static usart__data_register_empty_callback_t* p_data_register_empty = NULL; |
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| 52 | |||
| 53 | static usart__configuration_t configuration = |
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| 54 | { |
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| 55 | .mode = USART__MODE__ASYNCHRONOUS, |
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| 56 | .baudrate = USART__BAUDRATE__9600, |
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| 57 | .data_size = USART__DATA_SIZE__8_BITS, |
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| 58 | .stop_size = USART__STOP_SIZE__1_BIT, |
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| 59 | .parity = USART__PARITY__DISABLED |
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| 60 | }; |
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| 61 | |||
| 62 | static bool double_speed_is_set = false; |
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| 63 | |||
| 64 | /****************************************************************************** |
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| 65 | * Private function prototypes. |
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| 66 | ******************************************************************************/ |
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| 67 | |||
| 68 | /**************************************************************************//** |
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| 69 | * \fn static inline uint16_t usart0__compute_ubrr(void) |
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| 70 | * |
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| 71 | * \brief Compute UBRR register value. |
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| 72 | * |
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| 73 | * \return UBRR value. |
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| 74 | ******************************************************************************/ |
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| 75 | static inline |
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| 76 | uint16_t |
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| 77 | usart0__compute_ubrr |
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| 78 | ( |
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| 79 | void |
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| 80 | ); |
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| 81 | |||
| 82 | /****************************************************************************** |
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| 83 | * Public function definitions. |
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| 84 | ******************************************************************************/ |
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| 85 | |||
| 86 | /**************************************************************************//** |
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| 87 | * \fn void usart0__initialize(usart__configuration_t* p_configuration) |
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| 88 | * |
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| 89 | * \brief Initialize USART0. |
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| 90 | * |
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| 91 | * \param[in] p_configuration USART configuration. If null, default settings |
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| 92 | * will be used. |
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| 93 | * |
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| 94 | * Default settings: |
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| 95 | * - baudrate = 9600 bps; |
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| 96 | * - 8 data bits; |
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| 97 | * - 1 stop bit; |
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| 98 | * - no parity. |
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| 99 | ******************************************************************************/ |
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| 100 | void |
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| 101 | usart0__initialize |
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| 102 | ( |
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| 103 | usart__configuration_t* p_configuration |
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| 104 | ){ |
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| 105 | // If p_configuration is not null, use it! |
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| 106 | if (NULL != p_configuration) |
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| 107 | { |
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| 108 | configuration = *p_configuration; |
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| 109 | } |
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| 110 | |||
| 111 | // Set mode. |
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| 112 | usart0__set_mode(configuration.mode); |
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| 113 | |||
| 114 | // Set baud rate. |
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| 115 | usart0__set_baudrate(configuration.baudrate); |
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| 116 | usart0__set_double_speed(false); |
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| 117 | |||
| 118 | // Configure settings. |
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| 119 | usart0__set_data_size(configuration.data_size); |
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| 120 | usart0__set_stop_size(configuration.stop_size); |
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| 121 | usart0__set_parity(configuration.parity); |
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| 122 | } |
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| 123 | |||
| 124 | /**************************************************************************//** |
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| 125 | * \fn void usart0__set_baudrate(usart__baudrate_t baudrate) |
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| 126 | * |
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| 127 | * \brief Set USART0 baudrate. |
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| 128 | * |
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| 129 | * \param baudrate baudrate to set (in bauds per second) |
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| 130 | ******************************************************************************/ |
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| 131 | void |
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| 132 | usart0__set_baudrate |
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| 133 | ( |
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| 134 | usart__baudrate_t baudrate |
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| 135 | ){ |
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| 136 | configuration.baudrate = baudrate; |
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| 137 | |||
| 138 | uint16_t ubrr = usart0__compute_ubrr(); |
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| 139 | UBRR0H = (uint8_t)(ubrr >> 8); |
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| 140 | UBRR0L = (uint8_t)ubrr; |
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| 141 | } |
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| 142 | |||
| 143 | /**************************************************************************//** |
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| 144 | * \fn void usart0__set_mode(usart__mode_t usart_mode) |
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| 145 | * |
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| 146 | * \brief Set USART0 mode. |
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| 147 | * |
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| 148 | * \param usart_mode Mode to set. |
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| 149 | ******************************************************************************/ |
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| 150 | void |
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| 151 | usart0__set_mode |
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| 152 | ( |
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| 153 | usart__mode_t usart_mode |
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| 154 | ){ |
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| 155 | // Check the preconditions. |
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| 156 | assert(USART__MODE__INVALID > usart_mode); |
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| 157 | |||
| 158 | configuration.mode = usart_mode; |
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| 159 | |||
| 160 | switch (usart_mode) |
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| 161 | { |
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| 162 | case USART__MODE__ASYNCHRONOUS: |
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| 163 | { |
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| 164 | BIT__RST(UCSR0C, UMSEL01); |
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| 165 | BIT__RST(UCSR0C, UMSEL00); |
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| 166 | } |
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| 167 | break; |
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| 168 | |||
| 169 | case USART__MODE__SYNCHRONOUS: |
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| 170 | { |
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| 171 | BIT__RST(UCSR0C, UMSEL01); |
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| 172 | BIT__SET(UCSR0C, UMSEL00); |
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| 173 | } |
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| 174 | break; |
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| 175 | |||
| 176 | case USART__MODE__MASTER_SPI: |
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| 177 | { |
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| 178 | BIT__SET(UCSR0C, UMSEL01); |
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| 179 | BIT__SET(UCSR0C, UMSEL00); |
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| 180 | } |
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| 181 | break; |
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| 182 | |||
| 183 | case USART__MODE__INVALID: |
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| 184 | default: |
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| 185 | break; |
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| 186 | } |
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| 187 | } |
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| 188 | |||
| 189 | /**************************************************************************//** |
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| 190 | * \fn void usart0__set_data_size(usart__data_sizet data_size) |
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| 191 | * |
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| 192 | * \brief Set USART0 data size. |
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| 193 | * |
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| 194 | * \param data_size data size (in bits) |
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| 195 | ******************************************************************************/ |
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| 196 | void |
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| 197 | usart0__set_data_size |
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| 198 | ( |
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| 199 | usart__data_size_t data_size |
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| 200 | ){ |
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| 201 | configuration.data_size = data_size; |
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| 202 | |||
| 203 | switch (data_size) |
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| 204 | { |
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| 205 | case USART__DATA_SIZE__5_BITS: |
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| 206 | { |
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| 207 | BIT__RST(UCSR0B, UCSZ02); |
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| 208 | BIT__RST(UCSR0C, UCSZ01); |
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| 209 | BIT__RST(UCSR0C, UCSZ00); |
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| 210 | } |
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| 211 | break; |
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| 212 | |||
| 213 | case USART__DATA_SIZE__6_BITS: |
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| 214 | { |
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| 215 | BIT__RST(UCSR0B, UCSZ02); |
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| 216 | BIT__RST(UCSR0C, UCSZ01); |
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| 217 | BIT__SET(UCSR0C, UCSZ00); |
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| 218 | } |
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| 219 | break; |
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| 220 | |||
| 221 | case USART__DATA_SIZE__7_BITS: |
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| 222 | { |
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| 223 | BIT__RST(UCSR0B, UCSZ02); |
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| 224 | BIT__SET(UCSR0C, UCSZ01); |
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| 225 | BIT__RST(UCSR0C, UCSZ00); |
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| 226 | } |
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| 227 | break; |
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| 228 | |||
| 229 | case USART__DATA_SIZE__8_BITS: |
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| 230 | { |
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| 231 | BIT__RST(UCSR0B, UCSZ02); |
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| 232 | BIT__SET(UCSR0C, UCSZ01); |
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| 233 | BIT__SET(UCSR0C, UCSZ00); |
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| 234 | } |
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| 235 | break; |
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| 236 | |||
| 237 | case USART__DATA_SIZE__9_BITS: |
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| 238 | { |
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| 239 | BIT__SET(UCSR0B, UCSZ02); |
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| 240 | BIT__SET(UCSR0C, UCSZ01); |
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| 241 | BIT__SET(UCSR0C, UCSZ00); |
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| 242 | } |
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| 243 | break; |
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| 244 | |||
| 245 | default: |
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| 246 | break; |
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| 247 | } |
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| 248 | } |
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| 249 | |||
| 250 | /**************************************************************************//** |
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| 251 | * \fn void usart0__set_stop_size(usart__stop_size_t stop_size) |
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| 252 | * |
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| 253 | * \brief Set USART0 stop size. |
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| 254 | * |
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| 255 | * \param stop_size stop size (in bits) |
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| 256 | ******************************************************************************/ |
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| 257 | void |
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| 258 | usart0__set_stop_size |
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| 259 | ( |
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| 260 | usart__stop_size_t stop_size |
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| 261 | ){ |
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| 262 | configuration.stop_size = stop_size; |
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| 263 | |||
| 264 | if (USART__STOP_SIZE__1_BIT == stop_size) |
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| 265 | { |
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| 266 | BIT__RST(UCSR0C, USBS0); |
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| 267 | } |
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| 268 | else |
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| 269 | { |
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| 270 | BIT__SET(UCSR0C, USBS0); |
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| 271 | } |
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| 272 | } |
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| 273 | |||
| 274 | /**************************************************************************//** |
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| 275 | * \fn void usart0__set_parity(usart__parity_t parity) |
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| 276 | * |
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| 277 | * \brief Set USART0 parity. |
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| 278 | * |
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| 279 | * \param parity parity to set |
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| 280 | ******************************************************************************/ |
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| 281 | void |
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| 282 | usart0__set_parity |
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| 283 | ( |
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| 284 | usart__parity_t parity |
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| 285 | ){ |
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| 286 | configuration.parity = parity; |
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| 287 | |||
| 288 | switch (parity) |
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| 289 | { |
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| 290 | case USART__PARITY__DISABLED: |
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| 291 | { |
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| 292 | BIT__RST(UCSR0C, UPM01); |
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| 293 | BIT__RST(UCSR0C, UPM00); |
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| 294 | } |
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| 295 | break; |
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| 296 | |||
| 297 | case USART__PARITY__EVEN: |
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| 298 | { |
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| 299 | BIT__SET(UCSR0C, UPM01); |
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| 300 | BIT__RST(UCSR0C, UPM00); |
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| 301 | } |
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| 302 | break; |
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| 303 | |||
| 304 | case USART__PARITY__ODD: |
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| 305 | { |
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| 306 | BIT__SET(UCSR0C, UPM01); |
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| 307 | BIT__SET(UCSR0C, UPM00); |
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| 308 | } |
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| 309 | break; |
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| 310 | |||
| 311 | default: |
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| 312 | break; |
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| 313 | } |
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| 314 | } |
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| 315 | |||
| 316 | /**************************************************************************//** |
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| 317 | * \fn void usart0__set_double_speed(bool double_speed) |
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| 318 | * |
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| 319 | * \brief Set double speed. |
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| 320 | * |
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| 321 | * \param double_speed True to set double speed, false otherwise. |
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| 322 | ******************************************************************************/ |
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| 323 | void |
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| 324 | usart0__set_double_speed |
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| 325 | ( |
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| 326 | bool double_speed |
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| 327 | ){ |
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| 328 | double_speed_is_set = double_speed; |
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| 329 | |||
| 330 | if (double_speed_is_set) |
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| 331 | { |
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| 332 | BIT__SET(UCSR0A, U2X0); |
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| 333 | } |
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| 334 | else |
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| 335 | { |
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| 336 | BIT__RST(UCSR0A, U2X0); |
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| 337 | } |
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| 338 | } |
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| 339 | |||
| 340 | /**************************************************************************//** |
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| 341 | * \fn void usart0__enable_receiver(void) |
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| 342 | * |
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| 343 | * \brief Enable USART 0 receiver. |
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| 344 | ******************************************************************************/ |
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| 345 | void |
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| 346 | usart0__enable_receiver |
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| 347 | ( |
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| 348 | void |
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| 349 | ){ |
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| 350 | BIT__SET(UCSR0B, RXEN0); |
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| 351 | } |
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| 352 | |||
| 353 | /**************************************************************************//** |
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| 354 | * \fn void usart0__disable_receiver(void) |
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| 355 | * |
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| 356 | * \brief Disable USART 0 receiver. |
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| 357 | ******************************************************************************/ |
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| 358 | void |
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| 359 | usart0__disable_receiver |
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| 360 | ( |
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| 361 | void |
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| 362 | ){ |
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| 363 | BIT__RST(UCSR0B, RXEN0); |
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| 364 | } |
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| 365 | |||
| 366 | /**************************************************************************//** |
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| 367 | * \fn void usart0__enable_transmitter(void) |
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| 368 | * |
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| 369 | * \brief Enable USART 0 transmitter. |
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| 370 | ******************************************************************************/ |
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| 371 | void |
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| 372 | usart0__enable_transmitter |
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| 373 | ( |
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| 374 | void |
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| 375 | ){ |
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| 376 | BIT__SET(UCSR0B, TXEN0); |
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| 377 | } |
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| 378 | |||
| 379 | /**************************************************************************//** |
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| 380 | * \fn void usart0__disable_transmitter(void) |
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| 381 | * |
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| 382 | * \brief Disable USART 0 transmitter. |
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| 383 | ******************************************************************************/ |
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| 384 | void |
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| 385 | usart0__disable_transmitter |
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| 386 | ( |
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| 387 | void |
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| 388 | ){ |
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| 389 | BIT__RST(UCSR0B, TXEN0); |
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| 390 | } |
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| 391 | |||
| 392 | /**************************************************************************//** |
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| 393 | * \fn uint8_t usart0__receive_byte(void) |
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| 394 | * |
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| 395 | * \brief Receive a byte on USART0. |
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| 396 | * |
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| 397 | * \return received byte |
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| 398 | ******************************************************************************/ |
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| 399 | uint16_t |
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| 400 | usart0__receive_byte |
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| 401 | ( |
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| 402 | void |
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| 403 | ){ |
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| 404 | // Wait for data to be received. |
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| 405 | while (!(UCSR0A & (1 << RXC0))); |
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| 406 | |||
| 407 | // Get received data. |
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| 408 | uint16_t received_byte = UDR0; |
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| 409 | |||
| 410 | if (USART__DATA_SIZE__9_BITS == configuration.data_size) |
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| 411 | { |
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| 412 | // If 9-bit data size, get 9th bit. |
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| 413 | uint8_t resh = UCSR0B; |
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| 414 | resh = (resh >> 1) & 0x01; |
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| 415 | received_byte = (resh << 8) | received_byte; |
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| 416 | } |
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| 417 | |||
| 418 | // Return received data from buffer. |
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| 419 | return received_byte; |
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| 420 | } |
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| 421 | |||
| 422 | /**************************************************************************//** |
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| 423 | * \fn usart0__transmit_byte(uint8_t byte_to_transmit) |
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| 424 | * |
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| 425 | * \brief Transmit a byte on USART0. |
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| 426 | * |
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| 427 | * \param byte_to_transmit byte to transmit |
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| 428 | ******************************************************************************/ |
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| 429 | void |
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| 430 | usart0__transmit_byte |
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| 431 | ( |
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| 432 | uint16_t byte_to_transmit |
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| 433 | ){ |
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| 434 | // Wait for empty transmit buffer. |
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| 435 | while (!(UCSR0A & (1 << UDRE0))); |
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| 436 | |||
| 437 | if (USART__DATA_SIZE__9_BITS == configuration.data_size) |
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| 438 | { |
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| 439 | // If 9-bit data size, copy 9th bit to TXB80. |
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| 440 | UCSR0B &= ~(1 << TXB80); |
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| 441 | if (byte_to_transmit & 0x0100) |
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| 442 | { |
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| 443 | UCSR0B |= (1 << TXB80); |
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| 444 | } |
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| 445 | } |
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| 446 | |||
| 447 | // Put data into transmit buffer, sends the data. |
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| 448 | UDR0 = byte_to_transmit; |
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| 449 | } |
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| 450 | |||
| 451 | /**************************************************************************//** |
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| 452 | * \fn void usart0__flush(void) |
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| 453 | * |
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| 454 | * \brief Flush USART0 receiver buffer. |
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| 455 | ******************************************************************************/ |
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| 456 | void |
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| 457 | usart0__flush |
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| 458 | ( |
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| 459 | void |
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| 460 | ){ |
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| 461 | uint8_t dummy = 0; |
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| 462 | while (UCSR0A & (1 << RXC0)) |
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| 463 | { |
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| 464 | dummy = UDR0; |
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| 465 | } |
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| 466 | } |
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| 467 | |||
| 468 | /**************************************************************************//** |
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| 469 | * \fn void usart0__enable_rx_complete_interrupt(void) |
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| 470 | * |
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| 471 | * \brief Enable USART 0 receive complete interrupt. |
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| 472 | ******************************************************************************/ |
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| 473 | void |
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| 474 | usart0__enable_rx_complete_interrupt |
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| 475 | ( |
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| 476 | void |
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| 477 | ){ |
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| 478 | BIT__SET(UCSR0B, RXCIE0); |
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| 479 | sei(); |
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| 480 | } |
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| 481 | |||
| 482 | /**************************************************************************//** |
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| 483 | * \fn void usart0__disable_rx_complete_interrupt(void) |
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| 484 | * |
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| 485 | * \brief Disable USART 0 receive complete interrupt. |
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| 486 | ******************************************************************************/ |
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| 487 | void |
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| 488 | usart0__disable_rx_complete_interrupt |
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| 489 | ( |
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| 490 | void |
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| 491 | ){ |
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| 492 | BIT__RST(UCSR0B, RXCIE0); |
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| 493 | sei(); |
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| 494 | } |
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| 495 | |||
| 496 | /**************************************************************************//** |
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| 497 | * \fn void usart0__set_rx_complete_callback( |
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| 498 | * const usart__rx_complete_callback_t* p_callback) |
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| 499 | * |
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| 500 | * \brief Set a callback to call when receive byte complete interrupt is |
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| 501 | * generated. |
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| 502 | * |
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| 503 | * \param[in] p_callback Callback to set. |
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| 504 | ******************************************************************************/ |
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| 505 | void |
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| 506 | usart0__set_rx_complete_callback |
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| 507 | ( |
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| 508 | const usart__rx_complete_callback_t* p_callback |
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| 509 | ){ |
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| 510 | // Check the preconditions. |
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| 511 | assert(NULL != p_callback); |
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| 512 | |||
| 513 | p_rx_complete = p_callback; |
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| 514 | } |
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| 515 | |||
| 516 | /**************************************************************************//** |
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| 517 | * \fn void usart0__enable_tx_complete_interrupt(void) |
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| 518 | * |
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| 519 | * \brief Enable interrupt when TX complete. |
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| 520 | ******************************************************************************/ |
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| 521 | void |
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| 522 | usart0__enable_tx_complete_interrupt |
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| 523 | ( |
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| 524 | void |
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| 525 | ){ |
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| 526 | BIT__SET(UCSR0B, TXCIE0); |
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| 527 | sei(); |
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| 528 | } |
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| 529 | |||
| 530 | /**************************************************************************//** |
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| 531 | * \fn void usart0__disable_tx_complete_interrupt(void) |
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| 532 | * |
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| 533 | * \brief Disable interrupt when TX complete. |
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| 534 | ******************************************************************************/ |
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| 535 | void |
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| 536 | usart0__disable_tx_complete_interrupt |
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| 537 | ( |
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| 538 | void |
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| 539 | ){ |
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| 540 | BIT__RST(UCSR0B, TXCIE0); |
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| 541 | sei(); |
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| 542 | } |
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| 543 | |||
| 544 | /**************************************************************************//** |
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| 545 | * \fn void usart0__set_tx_complete_callback( |
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| 546 | * const usart__tx_complete_callback_t* p_callback) |
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| 547 | * |
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| 548 | * \brief Set a callback to call when TX is complete. |
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| 549 | * |
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| 550 | * \param[in] p_callback Function to call. |
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| 551 | ******************************************************************************/ |
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| 552 | void |
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| 553 | usart0__set_tx_complete_callback |
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| 554 | ( |
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| 555 | const usart__tx_complete_callback_t* p_callback |
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| 556 | ){ |
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| 557 | // Check the preconditions. |
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| 558 | assert(NULL != p_callback); |
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| 559 | |||
| 560 | p_tx_complete = p_callback; |
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| 561 | } |
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| 562 | |||
| 563 | /**************************************************************************//** |
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| 564 | * \fn void usart0__enable_data_register_empty_interrupt() |
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| 565 | * |
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| 566 | * \brief Enable interrupt when data register is empty. |
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| 567 | ******************************************************************************/ |
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| 568 | void |
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| 569 | usart0__enable_data_register_empty_interrupt |
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| 570 | ( |
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| 571 | void |
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| 572 | ){ |
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| 573 | BIT__SET(UCSR0B, UDRIE0); |
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| 574 | sei(); |
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| 575 | } |
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| 576 | |||
| 577 | /**************************************************************************//** |
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| 578 | * \fn void usart0__disable_data_register_empty_interrupt() |
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| 579 | * |
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| 580 | * \brief Disable interrupt when data register is empty. |
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| 581 | ******************************************************************************/ |
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| 582 | void |
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| 583 | usart0__disable_data_register_empty_interrupt |
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| 584 | ( |
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| 585 | void |
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| 586 | ){ |
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| 587 | BIT__RST(UCSR0B, UDRIE0); |
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| 588 | sei(); |
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| 589 | } |
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| 590 | |||
| 591 | /**************************************************************************//** |
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| 592 | * \fn void usart0__set_data_register_empty_callback( |
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| 593 | * const usart__data_register_empty_callback_t* p_callback) |
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| 594 | * |
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| 595 | * \brief Set a callback to call when data register is empty. |
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| 596 | * |
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| 597 | * \param[in] p_callback Function to call. |
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| 598 | ******************************************************************************/ |
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| 599 | void |
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| 600 | usart0__set_data_register_empty_callback |
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| 601 | ( |
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| 602 | const usart__data_register_empty_callback_t* p_callback |
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| 603 | ){ |
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| 604 | // Check the preconditions. |
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| 605 | assert(NULL != p_callback); |
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| 606 | |||
| 607 | p_data_register_empty = p_callback; |
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| 608 | } |
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| 609 | |||
| 610 | /****************************************************************************** |
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| 611 | * Private function definitions. |
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| 612 | ******************************************************************************/ |
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| 613 | |||
| 614 | /**************************************************************************//** |
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| 615 | * \fn static inline uint16_t usart0__compute_ubrr(void) |
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| 616 | * |
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| 617 | * \brief Compute UBRR register value. |
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| 618 | * |
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| 619 | * \return UBRR value. |
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| 620 | ******************************************************************************/ |
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| 621 | static inline |
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| 622 | uint16_t |
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| 623 | usart0__compute_ubrr |
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| 624 | ( |
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| 625 | void |
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| 626 | ){ |
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| 627 | uint16_t ubrr = 0; |
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| 628 | |||
| 629 | switch (configuration.mode) |
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| 630 | { |
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| 631 | case USART__MODE__ASYNCHRONOUS: |
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| 632 | { |
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| 633 | if (!double_speed_is_set) |
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| 634 | { |
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| 635 | ubrr = F_CPU / (16 * configuration.baudrate) - 1; |
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| 636 | } |
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| 637 | else |
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| 638 | { |
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| 639 | ubrr = F_CPU / (8 * configuration.baudrate) - 1; |
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| 640 | } |
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| 641 | } |
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| 642 | break; |
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| 643 | |||
| 644 | case USART__MODE__SYNCHRONOUS: |
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| 645 | { |
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| 646 | ubrr = F_CPU / (2 * configuration.baudrate) - 1; |
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| 647 | } |
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| 648 | break; |
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| 649 | |||
| 650 | case USART__MODE__MASTER_SPI: |
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| 651 | break; |
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| 652 | |||
| 653 | default: |
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| 654 | break; |
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| 655 | } |
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| 656 | |||
| 657 | return ubrr; |
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| 658 | } |
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| 659 | |||
| 660 | /****************************************************************************** |
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| 661 | * Interrupt vectors. |
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| 662 | ******************************************************************************/ |
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| 663 | |||
| 664 | /**************************************************************************//** |
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| 665 | * \fn ISR(USART_RX_vect) |
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| 666 | * |
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| 667 | * \brief RX interrupt vector. |
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| 668 | ******************************************************************************/ |
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| 669 | ISR(USART_RX_vect) |
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| 670 | { |
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| 671 | if (NULL != p_rx_complete) |
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| 672 | { |
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| 673 | p_rx_complete(); |
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| 674 | } |
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| 675 | } |
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| 676 | |||
| 677 | /**************************************************************************//** |
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| 678 | * \fn ISR(USART_TX_vect) |
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| 679 | * |
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| 680 | * \brief TX interrupt vector. |
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| 681 | ******************************************************************************/ |
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| 682 | ISR(USART_TX_vect) |
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| 683 | { |
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| 684 | if (NULL != p_tx_complete) |
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| 685 | { |
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| 686 | p_tx_complete(); |
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| 687 | } |
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| 688 | } |
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| 689 | |||
| 690 | /**************************************************************************//** |
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| 691 | * \fn ISR(USART_UDRE_vect) |
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| 692 | * |
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| 693 | * \brief Data register empty interrupt vector. |
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| 694 | ******************************************************************************/ |
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| 695 | ISR(USART_UDRE_vect) |
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| 696 | { |
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| 697 | if (NULL != p_data_register_empty) |
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| 698 | { |
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| 699 | p_data_register_empty(); |
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| 700 | } |
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| 701 | } |